18 lines
No EOL
372 B
Verilog
18 lines
No EOL
372 B
Verilog
module counter_test;
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reg reset = 0;
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initial begin
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#17 reset = 1;
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#11 reset = 0;
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#17 reset = 1;
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#11 reset = 0;
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#17 $finish;
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end
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reg clk = 0;
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always #5 clk = !clk;
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wire [7:0] value;
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counter c1(value, clk, reset);
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initial
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$monitor("Time = %t, Value = %h (%0d)", $time, value, value);
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endmodule |