Tahinli/Verilog
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Ahmet Kaan GÜMÜŞ b407d22c78 alu
2024-12-20 21:04:06 +03:00
00-hello_world feat: ✨ hello world 2024-10-25 15:20:43 +03:00
01-counter fix: 🐛 not exiting when counting finish 2024-11-13 23:51:42 +03:00
02-counter_with_enable feat: ✨ counter with enable 2024-10-25 15:34:10 +03:00
03-8_bit_random_counter feat: ✨ 8 bit lfsr 2024-11-12 23:59:35 +03:00
04-encoder_with_if feat: ✨ encoder using if 2024-11-27 23:00:32 +03:00
05-encoder_with_case feat: ✨ encoder using case 2024-11-27 23:00:53 +03:00
06-alu alu 2024-12-20 21:04:06 +03:00
.gitignore feat: ✨ encoder using if 2024-11-27 23:00:32 +03:00
LICENSE Initial commit 2024-10-25 13:33:55 +03:00
README.md docs: 📝 readme 2024-11-28 18:22:40 +03:00

README.md

Verilog

Most of the examples are coming from asic-world and icarus. Verilog is my university course and I'm studying from these websites. Since most of the logical modules are same in the world, I'm not able to make much more difference when I'm studying from there. Most of the time I just rewrite or create test benches. I really would love to make difference from these websites but it's kinda impossible. That's why I must say that it's not a very original repo.