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Ahmet Kaan GÜMÜŞ 2024-11-28 18:22:40 +03:00
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# Verilog
Most of the examples are coming from [asic-world](https://www.asic-world.com/) and [icarus](https://steveicarus.github.io/iverilog/usage/getting_started.html).
Verilog is my university course and I'm studying from these websites.
Since most of the logical modules are same in the world, I'm not able to make much more difference when I'm studying from there.
Most of the time I just rewrite or create test benches.
I really would love to make difference from these websites but it's kinda impossible.
That's why I must say that it's not a very original repo.