diff --git a/README.md b/README.md
index 1f510b3..7502534 100644
--- a/README.md
+++ b/README.md
@@ -1 +1,8 @@
-# Verilog
\ No newline at end of file
+# Verilog
+
+Most of the examples are coming from [asic-world](https://www.asic-world.com/) and [icarus](https://steveicarus.github.io/iverilog/usage/getting_started.html). 
+Verilog is my university course and I'm studying from these websites. 
+Since most of the logical modules are same in the world, I'm not able to make much more difference when I'm studying from there. 
+Most of the time I just rewrite or create test benches. 
+I really would love to make difference from these websites but it's kinda impossible.
+That's why I must say that it's not a very original repo.
\ No newline at end of file