From cba979bf0f0f7f82539c0827f55170e1505a140b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ahmet=20Kaan=20G=C3=9CM=C3=9C=C5=9E?=
 <96421894+Tahinli@users.noreply.github.com>
Date: Thu, 28 Nov 2024 18:22:40 +0300
Subject: [PATCH] docs: :memo: readme

---
 README.md | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/README.md b/README.md
index 1f510b3..7502534 100644
--- a/README.md
+++ b/README.md
@@ -1 +1,8 @@
-# Verilog
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+# Verilog
+
+Most of the examples are coming from [asic-world](https://www.asic-world.com/) and [icarus](https://steveicarus.github.io/iverilog/usage/getting_started.html). 
+Verilog is my university course and I'm studying from these websites. 
+Since most of the logical modules are same in the world, I'm not able to make much more difference when I'm studying from there. 
+Most of the time I just rewrite or create test benches. 
+I really would love to make difference from these websites but it's kinda impossible.
+That's why I must say that it's not a very original repo.
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