29 lines
No EOL
521 B
Verilog
29 lines
No EOL
521 B
Verilog
module alu_tb;
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parameter N = 32;
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reg [N-1:0] op_a;
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reg [N-1:0] op_b;
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reg [3:0] opcode;
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wire [N-1:0] result;
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initial begin
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opcode = 3'd0;
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op_a = 2;
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op_b = 3;
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#2 opcode = 4'd1;
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#2 opcode = 4'd2;
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#2 opcode = 4'd3;
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#2 opcode = 4'd4;
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#2 opcode = 4'd5;
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#2 opcode = 4'd6;
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#2 opcode = 4'd7;
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#2 opcode = 4'd8;
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#2 opcode = 4'd8;
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end
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ALU c1 (opcode, op_a, op_b, result);
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initial
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$monitor("Opcode = %h | Op A = %h | Op B = %h | Result = %h", opcode, op_a, op_b,result);
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endmodule |