51 lines
1.3 KiB
Verilog
51 lines
1.3 KiB
Verilog
module encoder_using_if(
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output_wire,
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input_wire,
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enable,
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);
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output [3:0] output_wire;
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input enable ;
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input [15:0] input_wire;
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reg [3:0] output_wire;
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always @ (enable or input_wire)
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begin
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output_wire = 0;
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if (enable) begin
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if (input_wire == 16'h0002) begin
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output_wire = 1;
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end if (input_wire == 16'h0004) begin
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output_wire = 2;
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end if (input_wire == 16'h0008) begin
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output_wire = 3;
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end if (input_wire == 16'h0010) begin
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output_wire = 4;
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end if (input_wire == 16'h0020) begin
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output_wire = 5;
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end if (input_wire == 16'h0040) begin
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output_wire = 6;
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end if (input_wire == 16'h0080) begin
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output_wire = 7;
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end if (input_wire == 16'h0100) begin
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output_wire = 8;
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end if (input_wire == 16'h0200) begin
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output_wire = 9;
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end if (input_wire == 16'h0400) begin
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output_wire = 10;
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end if (input_wire == 16'h0800) begin
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output_wire = 11;
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end if (input_wire == 16'h1000) begin
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output_wire = 12;
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end if (input_wire == 16'h2000) begin
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output_wire = 13;
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end if (input_wire == 16'h4000) begin
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output_wire = 14;
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end if (input_wire == 16'h8000) begin
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output_wire = 15;
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end
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end
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end
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endmodule
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