23 lines
No EOL
538 B
Verilog
23 lines
No EOL
538 B
Verilog
module counter_with_enable_tb;
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parameter WIDTH = 8;
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reg reset = 0;
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reg enable = 0;
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initial begin
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#17 reset = 1;
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#11 enable = 1;
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#17 reset = 0;
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#11 enable = 1;
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#17 reset = 1;
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#17 $stop;
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end
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reg clk = 0;
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always begin
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#1 clk = 0;
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#1 clk = 1;
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end
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wire[WIDTH-1:0] output_wire;
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counter_with_enable c1(output_wire, enable, clk, reset);
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initial
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$monitor("Time = %t, Value = %h (%0d)", $time, output_wire, output_wire);
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endmodule |