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feat: ✨ encoder using case

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Ahmet Kaan GÜMÜŞ 2024-11-27 23:00:53 +03:00
parent ec30809a8b
commit a50b672bc2
2 changed files with 84 additions and 0 deletions
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36
05-encoder_with_case/encoder_with_case.v Normal file
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module encoder_using_case(
output_wire,
input_wire,
enable,
);
output [3:0] output_wire;
input enable ;
input [15:0] input_wire;
reg [3:0] output_wire;
always @ (enable or input_wire)
begin
output_wire = 0;
if (enable) begin
case (input_wire)
16'h0002 : output_wire = 1;
16'h0004 : output_wire = 2;
16'h0008 : output_wire = 3;
16'h0010 : output_wire = 4;
16'h0020 : output_wire = 5;
16'h0040 : output_wire = 6;
16'h0080 : output_wire = 7;
16'h0100 : output_wire = 8;
16'h0200 : output_wire = 9;
16'h0400 : output_wire = 10;
16'h0800 : output_wire = 11;
16'h1000 : output_wire = 12;
16'h2000 : output_wire = 13;
16'h4000 : output_wire = 14;
16'h8000 : output_wire = 15;
endcase
end
end
endmodule

48
05-encoder_with_case/encoder_with_case_tb.v Normal file
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module encoder_using_if_test;
parameter INPUT_LENGTH = 16;
parameter OUTPUT_LENGTH = 4;
reg [INPUT_LENGTH-1:0] input_wire;
wire [OUTPUT_LENGTH-1:0] output_wire;
reg enable = 0;
initial begin
#1 input_wire <= 16'h0000;
#1 input_wire <= 16'h0002;
#1 input_wire <= 16'h0004;
#1 input_wire <= 16'h0008;
#1 input_wire <= 16'h0010;
#1 input_wire <= 16'h0020;
#1 input_wire <= 16'h0040;
#1 input_wire <= 16'h0080;
#1 input_wire <= 16'h0100;
#1 input_wire <= 16'h0200;
#1 input_wire <= 16'h0400;
#1 input_wire <= 16'h0800;
#1 input_wire <= 16'h1000;
#1 input_wire <= 16'h2000;
#1 input_wire <= 16'h4000;
#1 input_wire <= 16'h8000;
#1 input_wire <= 16'h0000;
#1 enable = 1;
#1 input_wire <= 16'h0002;
#1 input_wire <= 16'h0004;
#1 input_wire <= 16'h0008;
#1 input_wire <= 16'h0010;
#1 input_wire <= 16'h0020;
#1 input_wire <= 16'h0040;
#1 input_wire <= 16'h0080;
#1 input_wire <= 16'h0100;
#1 input_wire <= 16'h0200;
#1 input_wire <= 16'h0400;
#1 input_wire <= 16'h0800;
#1 input_wire <= 16'h1000;
#1 input_wire <= 16'h2000;
#1 input_wire <= 16'h4000;
#1 input_wire <= 16'h8000;
#1 $finish;
end
encoder_using_case c1(output_wire, input_wire, enable);
initial
$monitor("Time = %t, Input = %h (%0d), Output = %d (%0d)", $time, input_wire, input_wire, output_wire, output_wire);
endmodule