36 lines
828 B
Verilog
36 lines
828 B
Verilog
module encoder_using_case(
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output_wire,
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input_wire,
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enable,
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);
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output [3:0] output_wire;
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input enable ;
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input [15:0] input_wire;
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reg [3:0] output_wire;
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always @ (enable or input_wire)
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begin
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output_wire = 0;
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if (enable) begin
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case (input_wire)
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16'h0002 : output_wire = 1;
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16'h0004 : output_wire = 2;
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16'h0008 : output_wire = 3;
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16'h0010 : output_wire = 4;
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16'h0020 : output_wire = 5;
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16'h0040 : output_wire = 6;
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16'h0080 : output_wire = 7;
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16'h0100 : output_wire = 8;
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16'h0200 : output_wire = 9;
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16'h0400 : output_wire = 10;
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16'h0800 : output_wire = 11;
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16'h1000 : output_wire = 12;
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16'h2000 : output_wire = 13;
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16'h4000 : output_wire = 14;
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16'h8000 : output_wire = 15;
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endcase
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end
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end
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endmodule
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