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feat: ✨ encoder using if

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Ahmet Kaan GÜMÜŞ 2024-11-27 23:00:32 +03:00
parent 4401194b77
commit ec30809a8b
3 changed files with 101 additions and 1 deletions
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1
.gitignore vendored
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*.bin
.vscode/

51
04-encoder_with_if/encoder_with_if.v Normal file
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module encoder_using_if(
output_wire,
input_wire,
enable,
);
output [3:0] output_wire;
input enable ;
input [15:0] input_wire;
reg [3:0] output_wire;
always @ (enable or input_wire)
begin
output_wire = 0;
if (enable) begin
if (input_wire == 16'h0002) begin
output_wire = 1;
end if (input_wire == 16'h0004) begin
output_wire = 2;
end if (input_wire == 16'h0008) begin
output_wire = 3;
end if (input_wire == 16'h0010) begin
output_wire = 4;
end if (input_wire == 16'h0020) begin
output_wire = 5;
end if (input_wire == 16'h0040) begin
output_wire = 6;
end if (input_wire == 16'h0080) begin
output_wire = 7;
end if (input_wire == 16'h0100) begin
output_wire = 8;
end if (input_wire == 16'h0200) begin
output_wire = 9;
end if (input_wire == 16'h0400) begin
output_wire = 10;
end if (input_wire == 16'h0800) begin
output_wire = 11;
end if (input_wire == 16'h1000) begin
output_wire = 12;
end if (input_wire == 16'h2000) begin
output_wire = 13;
end if (input_wire == 16'h4000) begin
output_wire = 14;
end if (input_wire == 16'h8000) begin
output_wire = 15;
end
end
end
endmodule

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04-encoder_with_if/encoder_with_if_tb.v Normal file
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module encoder_using_if_test;
parameter INPUT_LENGTH = 16;
parameter OUTPUT_LENGTH = 4;
reg [INPUT_LENGTH-1:0] input_wire;
wire [OUTPUT_LENGTH-1:0] output_wire;
reg enable = 0;
initial begin
#1 input_wire <= 16'h0000;
#1 input_wire <= 16'h0002;
#1 input_wire <= 16'h0004;
#1 input_wire <= 16'h0008;
#1 input_wire <= 16'h0010;
#1 input_wire <= 16'h0020;
#1 input_wire <= 16'h0040;
#1 input_wire <= 16'h0080;
#1 input_wire <= 16'h0100;
#1 input_wire <= 16'h0200;
#1 input_wire <= 16'h0400;
#1 input_wire <= 16'h0800;
#1 input_wire <= 16'h1000;
#1 input_wire <= 16'h2000;
#1 input_wire <= 16'h4000;
#1 input_wire <= 16'h8000;
#1 input_wire <= 16'h0000;
#1 enable = 1;
#1 input_wire <= 16'h0002;
#1 input_wire <= 16'h0004;
#1 input_wire <= 16'h0008;
#1 input_wire <= 16'h0010;
#1 input_wire <= 16'h0020;
#1 input_wire <= 16'h0040;
#1 input_wire <= 16'h0080;
#1 input_wire <= 16'h0100;
#1 input_wire <= 16'h0200;
#1 input_wire <= 16'h0400;
#1 input_wire <= 16'h0800;
#1 input_wire <= 16'h1000;
#1 input_wire <= 16'h2000;
#1 input_wire <= 16'h4000;
#1 input_wire <= 16'h8000;
#1 $finish;
end
encoder_using_if c1(output_wire, input_wire, enable);
initial
$monitor("Time = %t, Input = %h (%0d), Output = %d (%0d)", $time, input_wire, input_wire, output_wire, output_wire);
endmodule