style: ✨ counter

.gitignore

@@ -0,0 +1 @@
+*.bin

01-counter/counter.v

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+module counter(out, clk, reset);
+    parameter WIDTH = 8;
+    output [WIDTH-1:0] out;
+    input clk, reset;
+    reg [WIDTH-1: 0] out;
+    wire clk, reset;
+
+    always @(posedge clk or posedge reset) begin
+        if (reset)
+            out <= 0;
+        else
+            out <= out + 1;
+    end
+endmodule

01-counter/counter_tb.v

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+module counter_test;
+    reg reset = 0;
+    initial begin
+        #17 reset = 1;
+        #11 reset = 0;
+        #17 reset = 1;
+        #11 reset = 0;
+        #17 $stop;
+    end
+
+    reg clk = 0;
+    always #5 clk = !clk;
+
+    wire [7:0] value;
+    counter c1(value, clk, reset);
+    initial
+        $monitor("Time = %t, Value = %h (%0d)", $time, value, value);
+endmodule