diff --git a/02-counter_with_enable/counter_with_enable.v b/02-counter_with_enable/counter_with_enable.v
new file mode 100644
index 0000000..d7a65f2
--- /dev/null
+++ b/02-counter_with_enable/counter_with_enable.v
@@ -0,0 +1,14 @@
+module counter_with_enable(out, enable, clk, reset);
+    parameter WIDTH = 8;
+    input enable, clk, reset;
+    output[WIDTH-1:0] out;
+    reg[WIDTH-1:0] out;
+
+    always @(posedge clk)begin
+        if (reset) begin
+            out <= 8'b0;
+        end else if(enable) begin
+            out <= out + 1;
+        end
+    end
+endmodule
\ No newline at end of file
diff --git a/02-counter_with_enable/counter_with_enable_tb.v b/02-counter_with_enable/counter_with_enable_tb.v
new file mode 100644
index 0000000..404a9bf
--- /dev/null
+++ b/02-counter_with_enable/counter_with_enable_tb.v
@@ -0,0 +1,23 @@
+module counter_with_enable_tb;
+    parameter WIDTH = 8;
+    reg reset = 0;
+    reg enable = 0;
+    initial begin
+        #17 reset = 1;
+        #11 enable = 1;
+        #17 reset = 0;
+        #11 enable = 1;
+        #17 reset = 1;
+        #17 $stop;
+    end
+
+    reg clk = 0;
+    always begin
+        #1 clk = 0;
+        #1 clk = 1;
+    end
+    wire[WIDTH-1:0] output_wire;
+    counter_with_enable c1(output_wire, enable, clk, reset);
+    initial 
+        $monitor("Time = %t, Value = %h (%0d)", $time, output_wire, output_wire);
+endmodule
\ No newline at end of file