feat: ✨ 8 bit lfsr

03-8_bit_random_counter/8_bit_random_counter.v

@@ -0,0 +1,27 @@
+`define WIDTH 8
+module linear_feedback_shift_register_updown (clk, reset, enable, up_down, count, overflow);
+input clk;
+input reset;
+input enable; 
+input up_down;
+
+output [`WIDTH-1 : 0] count;
+output overflow;
+
+reg [`WIDTH-1 : 0] count;
+
+assign overflow = (up_down) ? (count == {{`WIDTH-1{1'b0}}, 1'b1}) : 
+                              (count == {1'b1, {`WIDTH-1{1'b0}}}) ;
+
+always @(posedge clk)
+if (reset) 
+  count <= {`WIDTH{1'b0}};
+else if (enable) begin
+  if (up_down) begin
+    count <= {~(^(count & `WIDTH'b01100011)),count[`WIDTH-1:1]};
+  end else begin
+    count <= {count[`WIDTH-2:0],~(^(count &  `WIDTH'b10110001))};
+  end
+end
+
+endmodule

03-8_bit_random_counter/8_bit_random_counter_tb.v

@@ -0,0 +1,34 @@
+module linear_feedback_shift_register_updown_test_bench();
+ reg clk;
+ reg reset;
+ reg enable;
+ reg up_down;
+
+ wire [`WIDTH-1 : 0] count;
+ wire overflow;
+
+initial begin
+  $monitor("Reset %b Enable %b Updown %b Count %b Overflow %b",
+      reset,enable,up_down,count, overflow);
+  clk = 0;
+  reset = 1;
+  enable = 0;
+  up_down = 0;
+  #5 reset = 0;
+  #1 enable = 1;
+  #5 up_down = 1;
+  #30 $finish;
+end
+
+always #1 clk = ~clk;
+
+linear_feedback_shift_register_updown c1(
+.clk      ( clk      ),
+.reset    ( reset    ),
+.enable   ( enable   ),
+.up_down  ( up_down  ),
+.count    ( count    ),
+.overflow ( overflow )
+);
+
+endmodule