Verilog/01-counter/counter.v

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2024-10-25 15:20:56 +03:00
module counter(out, clk, reset);
parameter WIDTH = 8;
output [WIDTH-1:0] out;
input clk, reset;
reg [WIDTH-1: 0] out;
wire clk, reset;
always @(posedge clk or posedge reset) begin
if (reset)
out <= 0;
else
out <= out + 1;
end
endmodule